The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this disclosure and are not admitted to be prior art by inclusion in this section.
In modern memory chips or SoC chips which contain high density memories, the chip areas are dominated by memory bitcells and arrays. On the other hand, passive devices, such as high precision Poly/OD resistors in these chips, can be formed as parasitic devices with specific designed sheet resistance (Rs) values. A “fabless” design house company typically designs semiconductor devices, and then turns over manufacture of these devices to various manufacturers. Fabless design house companies would prefer to have the flexibility of multiple available manufacturers for a number of reasons including business leverage and cost competition. Thus, fabless design houses typically request foundries to provide footprint-compatible memory bitcells and logic devices (e.g., memory periphery transistors), and tune the processes so that the memory and logic transistors of the chip achieve the required electrical performance. Accordingly, it should be no problem to port these designs between foundries.
However, due to fundamental process technology differences (e.g., different equipment, dopants, materials, etc.) from one foundry to another, if the circuit design is such that the graphic design system (GDS) footprint is to remain the same and only modifications to the process are to be made in order to maintain the same Rs in order to facilitate memory design porting from one foundry to another, such often requires adding at least one extra masking operation to, for example, change the implant dosage for the desired Rs. In some cases, for polysilicon resistors, two masks may be required including one to remove underlying metal or alloy film in order to achieve a higher Rs. Needless to say, this adds process complexity and thus, negatively impacts the yield and cost of the manufacturing due to more manufacturing operations.
As an example, consider FIG. 1 which illustrates an example gate-last Hi-K Metal Gate (HKMG) assembly generally at 100. HKMG assembly 100 includes active devices in an area 102 adjacent shallow trench isolation (STI) region 104. Formed over STI region 104 is a high precision resistor which, in this case, comprises an un-silicided polysilicon resistor 106 including two silicided end portions 107. In the bottommost view, taken a long line A-A′ in the topmost view, it can be seen that the un-silicided polysilicon resistor 106 and corresponding end portions 107 are disposed atop a Hi-K protection metal or alloy layer 108 and a Hi-K layer 110. Also shown is an active device 112 in the form of a metal oxide semiconductor (MOS) capacitor that, together with resistor 106, form a resistance-capacitor (RC) network that can be included within a semiconductor chip, in accordance with various embodiments of the present disclosure. The RC network includes a silicon substrate 114 that is configured with the MOS capacitor. The MOS capacitor includes a well 116 that has been doped with one of either N-type or P-type dopants. The corners 118, 120 of the well 116 are further doped with the other type of dopant.
The MOS capacitor includes a high-k (where k is a dielectric constant and the high-k is with respect to the dielectric constant of silicon dioxide) gate oxide layer 122 that is provided at a top portion of the MOS capacitor. A metal gate 124 is provided over the high-k gate oxide layer 122 between spacers (not specifically designated). Contacts 126 for the MOS capacitor are provided and include silicide portions at the bottommost layer, a tungsten layer atop the silicide portions, and a metal layer atop the tungsten layer.
As noted above, in such designs, in order to achieve the desired Rs value for the high precision resistors, either an extra masking operation is utilized to change the implant dosage for the desired Rs, or two masks are needed including one additional mask to remove the underlying metal or alloy layer 108.